High-level analysis of physical design planning covers the allocation of input/outputs (IOs), diffused memories and location of R-cell memories within integrated circuit designs based on programmable platform devices, such as platform and structured application specific integrated circuits (ASICs). In a conventional design flow a designer decides: (i) where to place IOs, (ii) how to assign functional memories to diffused memories, and (iii) where to place R-cell memories. The decisions are made without the designer being able to see the various subsystems (blocks) and memory topology of the design. The designer typically guesses (or estimates) a size for each subsystem. Assignment and placement decisions are made based on the guess/estimate of the designer.
It is difficult for a designer, especially a novice one, to visualize how big each subsystem is in order to judge the optimum location and allocation for the subsystems. A bad assignment can be difficult to recognize because the effects are subtle (e.g., bad timing paths, congestion, etc.) and not always distinguishable from non-placement related issues. Conventional solutions involve either (i) the designer (or engineer) using his/her experience and design knowledge to place and assign the subsystems or (ii) a full floorplanning analysis that uses actual netlist data and actual cell area in a professional floorplanning tool.
The conventional solutions are unacceptable for two reasons. Relying on the designer to use experience and design knowledge to place and assign subsystems is not desirable because the engineer, even with expertise, can easily mis-estimate the layout and obtain sub-optimal results without being able to identify that the IO and memory allocation/placement played a role. Performing a full floorplanning analysis with actual netlist data and actual cell area data is only practical for application specific integrated circuit (ASIC) designs where a great deal of time is available to do full floorplanning. Also, the full floorplanning tools are very expensive and slow. The full benefit of full floorplanning is only realized with ASIC designs where the designer has full control over diffused memory placement. For designs involving programmable platform devices, a full floorplanning analysis is not practical because the floorplanning tools can cost many times more than the entire engineering costs for the designs.
It would be desirable to have a floorplan visualization method and/or tool that does not have the disadvantages of the conventional solutions.